CDC Analysis Skill Overview Expert skill for Clock Domain Crossing (CDC) analysis and synchronizer design, ensuring metastability-safe multi-clock FPGA designs. Capabilities - Identify all clock domain crossings in RTL - Design 2FF and 3FF synchronizers with ASYNC REG - Implement Gray code counters for async FIFOs - Design handshake protocols (req-ack, valid-ready) - Calculate MTBF for synchronizers - Generate CDC constraints (set false path, set max delay) - Detect CDC violations (reconvergence, data stability) - Support Xilinx CDC-aware design flows Target Processes - cdc-design.js - reset-…