HDL Simulation Skill Overview Expert skill for HDL simulation across multiple simulators, enabling comprehensive functional verification of FPGA designs. Capabilities - Generate simulation scripts (do files, tcl) - Configure ModelSim/Questa simulations - Configure Vivado Simulator (xsim) - Configure VCS and Xcelium simulations - Analyze waveforms for debugging - Generate VCD and FSDB dumps - Configure code coverage collection - Support mixed-language simulation Target Processes - functional-simulation.js - testbench-development.js - uvm-testbench.js - constrained-random-verification.js Usage…