Customize PCIe (per-controller status / lanes / speed) Overview PCIe on Tegra264 (Thor, ) and Tegra234 (Orin, ) is split across multiple controllers that share the UPHY lane pool with USB3 / MGBE / UFS. Each controller's runtime behavior is determined by two surfaces, both required : | Surface | Target | Authoritative for | |---|---|---| | ODMDATA (+ , , , ) | in BPMP DTB | UPHY lane power, refclk gating, controller-side power rails | | Kernel-DT overlay on | in kernel DTB | Kernel probe, lane width, link speed, RC/EP mode | Skipping the kernel overlay on a disable lets the kernel probe a pow…