rtl-linting — Skillopedia

RTL Linting Skill Expert skill for RTL code quality checking and linting using Verible, SpyGlass, and vendor tools. Provides comprehensive code analysis for synthesis issues, coding style, CDC violations, and best practice enforcement. Overview The RTL Linting skill enables comprehensive RTL code quality checking, supporting: - SpyGlass/Ascent lint rule execution - Verible SystemVerilog linting and formatting - Vivado and Quartus lint checks - Synthesis coding issue detection - Inferred latch identification - Clock domain violation checking - Reset handling verification - Naming convention en…

)\n\nif [ -n \"$STAGED_SV\" ]; then\n verible-verilog-lint $STAGED_SV\n if [ $? -ne 0 ]; then\n echo \"Lint errors found. Fix before committing.\"\n exit 1\n fi\nfi\n```\n\n### Process Integration\n\nThe RTL Linting skill integrates with these processes:\n\n- `verilog-systemverilog-design.js` - SV development\n- `synthesis-optimization.js` - Pre-synthesis checks\n- `cdc-design.js` - CDC verification\n- `design-for-testability.js` - Testability checks\n\n## Troubleshooting\n\n### Common Issues\n\n| Issue | Cause | Solution |\n|-------|-------|----------|\n| False positive | Too strict rule | Add waiver with reason |\n| Missing file | Include path wrong | Check -I include paths |\n| Parse error | Syntax issue | Fix syntax or update tool |\n| Slow analysis | Large codebase | Run incremental lint |\n\n### Validation Commands\n\n```bash\n# Check Verible version\nverible-verilog-lint --version\n\n# Test single file\nverible-verilog-lint --rules=+all src/test.sv\n\n# List available rules\nverible-verilog-lint --help_rules\n\n# Verify waiver file\ncat waivers.yaml | python -c \"import yaml,sys; yaml.safe_load(sys.stdin)\"\n```\n\n## Best Practices\n\n1. **Run early, run often** - Lint on every commit\n2. **Fix errors first** - Block on errors in CI\n3. **Track trends** - Monitor warning counts over time\n4. **Document waivers** - Require justification for every waiver\n5. **Review periodically** - Audit waivers quarterly\n\n## MCP Server Integration\n\nThis skill can leverage the following MCP servers:\n\n| Server | Purpose |\n|--------|---------|\n| verible-mcp | SystemVerilog linting and formatting |\n| MCP4EDA | Design rule checking |\n\n## References\n\n- [Verible Documentation](https://chipsalliance.github.io/verible/)\n- [Verible GitHub](https://github.com/chipsalliance/verible)\n- [Xilinx DRC Reference](https://docs.xilinx.com/r/en-US/ug906-vivado-design-analysis)\n- [SpyGlass User Guide](https://www.synopsys.com/verification/static-and-formal-verification/spyglass.html)\n\n## See Also\n\n- [SKILL.md](./SKILL.md) - Full skill definition\n- [Verilog/SystemVerilog Design Process](../../verilog-systemverilog-design.js)\n- [Synthesis Optimization Process](../../synthesis-optimization.js)\n","content_type":"text/markdown; charset=utf-8","language":"markdown","size":6781,"content_sha256":"6551e60983db374ebc0b215e71845f340068dc2c01b0463f1fe570e3814d90ed"}],"content_json":{"type":"doc","content":[{"type":"heading","attrs":{"level":1},"content":[{"text":"RTL Linting Skill","type":"text"}]},{"type":"paragraph","content":[{"text":"Expert skill for RTL code quality checking and linting using Verible, SpyGlass, and vendor tools. Provides comprehensive code analysis for synthesis issues, coding style, CDC violations, and best practice enforcement.","type":"text"}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Overview","type":"text"}]},{"type":"paragraph","content":[{"text":"The RTL Linting skill enables comprehensive RTL code quality checking, supporting:","type":"text"}]},{"type":"bullet_list","content":[{"type":"list_item","content":[{"type":"paragraph","content":[{"text":"SpyGlass/Ascent lint rule execution","type":"text"}]}]},{"type":"list_item","content":[{"type":"paragraph","content":[{"text":"Verible SystemVerilog linting and formatting","type":"text"}]}]},{"type":"list_item","content":[{"type":"paragraph","content":[{"text":"Vivado and Quartus lint checks","type":"text"}]}]},{"type":"list_item","content":[{"type":"paragraph","content":[{"text":"Synthesis coding issue detection","type":"text"}]}]},{"type":"list_item","content":[{"type":"paragraph","content":[{"text":"Inferred latch identification","type":"text"}]}]},{"type":"list_item","content":[{"type":"paragraph","content":[{"text":"Clock domain violation checking","type":"text"}]}]},{"type":"list_item","content":[{"type":"paragraph","content":[{"text":"Reset handling verification","type":"text"}]}]},{"type":"list_item","content":[{"type":"paragraph","content":[{"text":"Naming convention enforcement","type":"text"}]}]},{"type":"list_item","content":[{"type":"paragraph","content":[{"text":"Lint report generation and waiver management","type":"text"}]}]}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Capabilities","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"text":"1. Verible Linting","type":"text"}]},{"type":"paragraph","content":[{"text":"Run Verible SystemVerilog lint checks:","type":"text"}]},{"type":"code_block","attrs":{"wrap":false,"language":"bash"},"content":[{"text":"# Run all default lint rules\nverible-verilog-lint src/*.sv\n\n# Run with specific rules\nverible-verilog-lint --rules=no-trailing-spaces,line-length src/*.sv\n\n# Generate machine-readable output\nverible-verilog-lint --format=json src/*.sv > lint_report.json\n\n# Use rules configuration file\nverible-verilog-lint --rules_config=.verible.rules src/*.sv\n\n# Autofix where possible\nverible-verilog-lint --autofix=yes src/*.sv","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"text":"2. Verible Rules Configuration","type":"text"}]},{"type":"paragraph","content":[{"text":"Configure Verible lint rules:","type":"text"}]},{"type":"code_block","attrs":{"wrap":false,"language":""},"content":[{"text":"# .verible.rules\n\n# Enable rules\n+line-length\n+no-trailing-spaces\n+no-tabs\n+posix-eof\n\n# Disable rules\n-endif-comment\n-explicit-begin\n\n# Configure rule parameters\nline-length=length:120\n\n# Waiver syntax\n# waive:rule_name:reason","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"text":"3. Common Lint Checks","type":"text"}]},{"type":"paragraph","content":[{"text":"Detect common RTL issues:","type":"text"}]},{"type":"code_block","attrs":{"wrap":false,"language":"systemverilog"},"content":[{"text":"// ISSUE: Inferred latch (incomplete if-else)\nalways_comb begin\n if (sel)\n output = a;\n // Missing else - LATCH INFERRED\nend\n\n// FIX: Complete all branches\nalways_comb begin\n if (sel)\n output = a;\n else\n output = b;\nend\n\n// ISSUE: Blocking assignment in sequential block\nalways_ff @(posedge clk) begin\n temp = data; // WRONG: blocking in always_ff\n result \u003c= temp;\nend\n\n// FIX: Use non-blocking\nalways_ff @(posedge clk) begin\n temp \u003c= data; // CORRECT\n result \u003c= temp;\nend\n\n// ISSUE: Missing sensitivity list item\nalways @(a or b) begin // c missing!\n result = a & b | c;\nend\n\n// FIX: Use always_comb or @(*)\nalways_comb begin\n result = a & b | c;\nend\n\n// ISSUE: Case without default\nalways_comb begin\n case (sel)\n 2'b00: out = a;\n 2'b01: out = b;\n 2'b10: out = c;\n // Missing default - potential latch\n endcase\nend\n\n// FIX: Add default case\nalways_comb begin\n case (sel)\n 2'b00: out = a;\n 2'b01: out = b;\n 2'b10: out = c;\n default: out = '0;\n endcase\nend","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"text":"4. Clock Domain Crossing Checks","type":"text"}]},{"type":"paragraph","content":[{"text":"Detect CDC violations:","type":"text"}]},{"type":"code_block","attrs":{"wrap":false,"language":"systemverilog"},"content":[{"text":"// ISSUE: Unsynchronized CDC\nalways_ff @(posedge clk_b) begin\n data_b \u003c= data_a; // Direct crossing - CDC VIOLATION\nend\n\n// FIX: Add synchronizer\nlogic [1:0] sync_reg;\n(* ASYNC_REG = \"TRUE\" *)\nalways_ff @(posedge clk_b) begin\n sync_reg \u003c= {sync_reg[0], signal_a};\nend\nassign signal_b = sync_reg[1];\n\n// ISSUE: Multi-bit CDC without gray coding\nalways_ff @(posedge clk_b) begin\n ptr_b \u003c= ptr_a; // Multi-bit direct - DATA COHERENCY ISSUE\nend\n\n// FIX: Gray code for multi-bit CDC\nlogic [3:0] ptr_gray_a;\nassign ptr_gray_a = ptr_a ^ (ptr_a >> 1); // Binary to Gray\n\n(* ASYNC_REG = \"TRUE\" *)\nlogic [3:0] ptr_gray_sync [2];\nalways_ff @(posedge clk_b) begin\n ptr_gray_sync[0] \u003c= ptr_gray_a;\n ptr_gray_sync[1] \u003c= ptr_gray_sync[0];\nend","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"text":"5. Reset Handling Checks","type":"text"}]},{"type":"paragraph","content":[{"text":"Verify proper reset usage:","type":"text"}]},{"type":"code_block","attrs":{"wrap":false,"language":"systemverilog"},"content":[{"text":"// ISSUE: Missing reset\nalways_ff @(posedge clk) begin\n counter \u003c= counter + 1; // No reset - INITIALIZATION ISSUE\nend\n\n// FIX: Add reset\nalways_ff @(posedge clk or negedge rst_n) begin\n if (!rst_n)\n counter \u003c= '0;\n else\n counter \u003c= counter + 1;\nend\n\n// ISSUE: Async reset on BRAM (won't synthesize)\n(* RAM_STYLE = \"block\" *)\nlogic [7:0] mem [256];\n\nalways_ff @(posedge clk or negedge rst_n) begin\n if (!rst_n)\n mem \u003c= '{default: '0}; // Can't reset BRAM!\n else if (wr_en)\n mem[addr] \u003c= data;\nend\n\n// FIX: Remove async reset from BRAM\nalways_ff @(posedge clk) begin\n if (wr_en)\n mem[addr] \u003c= data;\nend","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"text":"6. Naming Convention Checks","type":"text"}]},{"type":"paragraph","content":[{"text":"Enforce coding standards:","type":"text"}]},{"type":"code_block","attrs":{"wrap":false,"language":"systemverilog"},"content":[{"text":"// Recommended naming conventions\n\n// Signals\nlogic data_valid; // snake_case for signals\nlogic [7:0] byte_count; // descriptive names\n\n// Parameters\nparameter int DATA_WIDTH = 8; // UPPER_CASE for parameters\nlocalparam int ADDR_BITS = 4; // UPPER_CASE for localparams\n\n// Types\ntypedef enum logic [1:0] {\n STATE_IDLE, // UPPER_CASE for enum values\n STATE_RUN,\n STATE_DONE\n} state_t; // _t suffix for types\n\n// Modules\nmodule data_processor ( // snake_case for modules\n // ...\n);\n\n// Interfaces\ninterface axi_stream_if; // _if suffix for interfaces\n\n// Clock and reset naming\ninput logic clk, // clk for clocks\ninput logic clk_200mhz, // clk_ prefix with frequency\ninput logic rst_n, // rst_n for active-low reset\ninput logic areset_n, // areset_n for async reset","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"text":"7. Vivado Lint Messages","type":"text"}]},{"type":"paragraph","content":[{"text":"Handle Vivado synthesis warnings:","type":"text"}]},{"type":"code_block","attrs":{"wrap":false,"language":"tcl"},"content":[{"text":"# Run synthesis with warning report\nsynth_design -top top_module -part xc7a200t-2-fbg484\n\n# Check for critical warnings\nreport_drc -file drc_report.txt\nreport_methodology -file methodology_report.txt\n\n# Common Vivado warnings to address:\n# [Synth 8-327] - Inferring latch\n# [Synth 8-3332] - Sequential element unused\n# [Synth 8-6014] - Unused sequential element removed\n# [Synth 8-3919] - Null assignment to signal\n# [Synth 8-5534] - Missing connection to port","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"text":"8. Lint Report Generation","type":"text"}]},{"type":"paragraph","content":[{"text":"Generate comprehensive lint reports:","type":"text"}]},{"type":"code_block","attrs":{"wrap":false,"language":"python"},"content":[{"text":"# lint_report.py\nimport json\nfrom dataclasses import dataclass\nfrom typing import List\n\n@dataclass\nclass LintViolation:\n file: str\n line: int\n rule: str\n severity: str # error, warning, info\n message: str\n waived: bool = False\n waiver_reason: str = \"\"\n\ndef generate_lint_report(violations: List[LintViolation]) -> dict:\n \"\"\"Generate structured lint report.\"\"\"\n report = {\n \"summary\": {\n \"total\": len(violations),\n \"errors\": sum(1 for v in violations if v.severity == \"error\"),\n \"warnings\": sum(1 for v in violations if v.severity == \"warning\"),\n \"waived\": sum(1 for v in violations if v.waived)\n },\n \"by_rule\": {},\n \"by_file\": {},\n \"violations\": []\n }\n\n for v in violations:\n # Group by rule\n if v.rule not in report[\"by_rule\"]:\n report[\"by_rule\"][v.rule] = []\n report[\"by_rule\"][v.rule].append(v.__dict__)\n\n # Group by file\n if v.file not in report[\"by_file\"]:\n report[\"by_file\"][v.file] = []\n report[\"by_file\"][v.file].append(v.__dict__)\n\n # Full list\n report[\"violations\"].append(v.__dict__)\n\n return report","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"text":"9. Waiver Management","type":"text"}]},{"type":"paragraph","content":[{"text":"Create and manage lint waivers:","type":"text"}]},{"type":"code_block","attrs":{"wrap":false,"language":"tcl"},"content":[{"text":"# waivers.tcl - SpyGlass waiver format\n\n# Waive specific instance\nwaive -rule STARC05-2.1.1.3 \\\n -msg \"Unregistered async input\" \\\n -instance \"top/async_input_sync\" \\\n -reason \"Synchronizer follows this register\"\n\n# Waive by file pattern\nwaive -rule W116 \\\n -file \"*/tb/*\" \\\n -reason \"Testbench code - not synthesized\"\n\n# Waive with comment\nwaive -rule STARC-2.1.3.1 \\\n -msg \"Latch inferred\" \\\n -instance \"debug_module/state_latch\" \\\n -reason \"Intentional latch for debug state capture\"","type":"text"}]},{"type":"code_block","attrs":{"wrap":false,"language":"yaml"},"content":[{"text":"# waivers.yaml - Alternative format\nwaivers:\n - rule: \"inferred-latch\"\n file: \"src/debug_capture.sv\"\n line: 42\n reason: \"Intentional latch for edge detection\"\n author: \"jdoe\"\n date: \"2026-01-24\"\n\n - rule: \"multi-bit-cdc\"\n instance: \"fifo_inst/wr_ptr_sync\"\n reason: \"Gray-coded pointer, safe CDC pattern\"\n author: \"jdoe\"\n date: \"2026-01-24\"","type":"text"}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Process Integration","type":"text"}]},{"type":"paragraph","content":[{"text":"This skill integrates with the following processes:","type":"text"}]},{"type":"table","attrs":{"layout":null},"content":[{"type":"tr","content":[{"type":"th","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"Process","type":"text"}]}]},{"type":"th","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"Integration Point","type":"text"}]}]}]},{"type":"tr","content":[{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"vhdl-module-development.js","type":"text","marks":[{"type":"code_inline"}]}]}]},{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"VHDL code quality","type":"text"}]}]}]},{"type":"tr","content":[{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"verilog-systemverilog-design.js","type":"text","marks":[{"type":"code_inline"}]}]}]},{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"Verilog/SV lint","type":"text"}]}]}]},{"type":"tr","content":[{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"synthesis-optimization.js","type":"text","marks":[{"type":"code_inline"}]}]}]},{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"Pre-synthesis checks","type":"text"}]}]}]},{"type":"tr","content":[{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"cdc-design.js","type":"text","marks":[{"type":"code_inline"}]}]}]},{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"CDC lint rules","type":"text"}]}]}]}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Workflow","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"text":"1. Configure Lint Rules","type":"text"}]},{"type":"code_block","attrs":{"wrap":false,"language":"bash"},"content":[{"text":"# Create Verible rules file\ncat > .verible.rules \u003c\u003c 'EOF'\n+line-length=length:120\n+no-trailing-spaces\n+no-tabs\n+posix-eof\n+explicit-parameter-storage-type\n+proper-parameter-type\n-endif-comment\nEOF","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"text":"2. Run Lint Checks","type":"text"}]},{"type":"code_block","attrs":{"wrap":false,"language":"bash"},"content":[{"text":"# Run Verible lint\nverible-verilog-lint --rules_config=.verible.rules src/*.sv\n\n# Run with JSON output\nverible-verilog-lint --rules_config=.verible.rules --format=json src/*.sv > lint.json","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"text":"3. Review and Fix","type":"text"}]},{"type":"code_block","attrs":{"wrap":false,"language":"bash"},"content":[{"text":"# Auto-format code\nverible-verilog-format --inplace src/*.sv\n\n# Review remaining issues\ncat lint.json | jq '.[] | select(.severity == \"error\")'","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"text":"4. Apply Waivers","type":"text"}]},{"type":"code_block","attrs":{"wrap":false,"language":"bash"},"content":[{"text":"# Add waivers for known issues\n# Document waiver reason in waivers.yaml","type":"text"}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Output Schema","type":"text"}]},{"type":"code_block","attrs":{"wrap":false,"language":"json"},"content":[{"text":"{\n \"lintResults\": {\n \"summary\": {\n \"totalFiles\": 25,\n \"filesWithIssues\": 8,\n \"totalViolations\": 42,\n \"errors\": 3,\n \"warnings\": 35,\n \"info\": 4,\n \"waived\": 5\n },\n \"byRule\": {\n \"inferred-latch\": {\n \"count\": 3,\n \"severity\": \"error\",\n \"violations\": [\n { \"file\": \"src/fsm.sv\", \"line\": 45, \"message\": \"...\" }\n ]\n },\n \"line-length\": {\n \"count\": 20,\n \"severity\": \"warning\",\n \"violations\": [...]\n }\n },\n \"byFile\": {\n \"src/fsm.sv\": {\n \"errors\": 2,\n \"warnings\": 5,\n \"violations\": [...]\n }\n }\n },\n \"waivers\": [\n { \"rule\": \"multi-bit-cdc\", \"instance\": \"fifo/ptr\", \"reason\": \"Gray coded\" }\n ],\n \"recommendations\": [\n \"Fix 3 errors before synthesis\",\n \"Review 35 warnings for code quality\",\n \"Consider enabling additional rules for CDC\"\n ],\n \"artifacts\": [\n \"reports/lint_summary.txt\",\n \"reports/lint_details.json\",\n \"waivers/approved_waivers.yaml\"\n ]\n}","type":"text"}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Common Lint Rules","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"text":"Critical (Must Fix)","type":"text"}]},{"type":"table","attrs":{"layout":null},"content":[{"type":"tr","content":[{"type":"th","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"Rule","type":"text"}]}]},{"type":"th","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"Description","type":"text"}]}]}]},{"type":"tr","content":[{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"inferred-latch","type":"text"}]}]},{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"Incomplete combinational assignment","type":"text"}]}]}]},{"type":"tr","content":[{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"blocking-in-ff","type":"text"}]}]},{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"Blocking assignment in always_ff","type":"text"}]}]}]},{"type":"tr","content":[{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"multi-bit-cdc","type":"text"}]}]},{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"Unprotected multi-bit CDC","type":"text"}]}]}]},{"type":"tr","content":[{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"missing-reset","type":"text"}]}]},{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"Register without reset","type":"text"}]}]}]},{"type":"tr","content":[{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"sensitivity-list","type":"text"}]}]},{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"Incomplete sensitivity list","type":"text"}]}]}]}]},{"type":"heading","attrs":{"level":3},"content":[{"text":"Warning (Should Fix)","type":"text"}]},{"type":"table","attrs":{"layout":null},"content":[{"type":"tr","content":[{"type":"th","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"Rule","type":"text"}]}]},{"type":"th","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"Description","type":"text"}]}]}]},{"type":"tr","content":[{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"line-length","type":"text"}]}]},{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"Line exceeds maximum length","type":"text"}]}]}]},{"type":"tr","content":[{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"trailing-spaces","type":"text"}]}]},{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"Trailing whitespace","type":"text"}]}]}]},{"type":"tr","content":[{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"no-tabs","type":"text"}]}]},{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"Tab characters in source","type":"text"}]}]}]},{"type":"tr","content":[{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"unused-signal","type":"text"}]}]},{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"Declared but unused signal","type":"text"}]}]}]},{"type":"tr","content":[{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"duplicate-condition","type":"text"}]}]},{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"Same condition in if/case","type":"text"}]}]}]}]},{"type":"heading","attrs":{"level":3},"content":[{"text":"Style (Recommended)","type":"text"}]},{"type":"table","attrs":{"layout":null},"content":[{"type":"tr","content":[{"type":"th","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"Rule","type":"text"}]}]},{"type":"th","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"Description","type":"text"}]}]}]},{"type":"tr","content":[{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"naming-convention","type":"text"}]}]},{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"Signal/module naming","type":"text"}]}]}]},{"type":"tr","content":[{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"explicit-width","type":"text"}]}]},{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"Explicit bit widths","type":"text"}]}]}]},{"type":"tr","content":[{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"port-order","type":"text"}]}]},{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"Port declaration order","type":"text"}]}]}]},{"type":"tr","content":[{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"comment-style","type":"text"}]}]},{"type":"td","attrs":{"colspan":1,"rowspan":1,"colwidth":null,"alignment":""},"content":[{"type":"paragraph","content":[{"text":"Comment formatting","type":"text"}]}]}]}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Best Practices","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"text":"Lint Integration","type":"text"}]},{"type":"bullet_list","content":[{"type":"list_item","content":[{"type":"paragraph","content":[{"text":"Run lint in CI/CD pipeline","type":"text"}]}]},{"type":"list_item","content":[{"type":"paragraph","content":[{"text":"Block merge on errors","type":"text"}]}]},{"type":"list_item","content":[{"type":"paragraph","content":[{"text":"Track warning trends","type":"text"}]}]},{"type":"list_item","content":[{"type":"paragraph","content":[{"text":"Review waivers periodically","type":"text"}]}]}]},{"type":"heading","attrs":{"level":3},"content":[{"text":"Code Quality","type":"text"}]},{"type":"bullet_list","content":[{"type":"list_item","content":[{"type":"paragraph","content":[{"text":"Fix errors immediately","type":"text"}]}]},{"type":"list_item","content":[{"type":"paragraph","content":[{"text":"Address warnings systematically","type":"text"}]}]},{"type":"list_item","content":[{"type":"paragraph","content":[{"text":"Use autoformat for style","type":"text"}]}]},{"type":"list_item","content":[{"type":"paragraph","content":[{"text":"Document intentional deviations","type":"text"}]}]}]},{"type":"heading","attrs":{"level":3},"content":[{"text":"Waiver Management","type":"text"}]},{"type":"bullet_list","content":[{"type":"list_item","content":[{"type":"paragraph","content":[{"text":"Require waiver justification","type":"text"}]}]},{"type":"list_item","content":[{"type":"paragraph","content":[{"text":"Review waivers in code review","type":"text"}]}]},{"type":"list_item","content":[{"type":"paragraph","content":[{"text":"Audit waivers quarterly","type":"text"}]}]},{"type":"list_item","content":[{"type":"paragraph","content":[{"text":"Remove stale waivers","type":"text"}]}]}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"References","type":"text"}]},{"type":"bullet_list","content":[{"type":"list_item","content":[{"type":"paragraph","content":[{"text":"Verible Documentation: https://chipsalliance.github.io/verible/","type":"text"}]}]},{"type":"list_item","content":[{"type":"paragraph","content":[{"text":"SpyGlass User Guide","type":"text"}]}]},{"type":"list_item","content":[{"type":"paragraph","content":[{"text":"Xilinx UG901: Vivado Synthesis (DRC)","type":"text"}]}]},{"type":"list_item","content":[{"type":"paragraph","content":[{"text":"Intel Quartus Prime Lint Guidelines","type":"text"}]}]}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"See Also","type":"text"}]},{"type":"bullet_list","content":[{"type":"list_item","content":[{"type":"paragraph","content":[{"text":"verilog-systemverilog-design.js","type":"text","marks":[{"type":"code_inline"}]},{"text":" - Verilog/SV development","type":"text"}]}]},{"type":"list_item","content":[{"type":"paragraph","content":[{"text":"synthesis-optimization.js","type":"text","marks":[{"type":"code_inline"}]},{"text":" - Synthesis preparation","type":"text"}]}]},{"type":"list_item","content":[{"type":"paragraph","content":[{"text":"SK-005: CDC Analysis skill","type":"text"}]}]},{"type":"list_item","content":[{"type":"paragraph","content":[{"text":"AG-001: RTL Design Expert agent","type":"text"}]}]}]},{"type":"hr","attrs":{"markup":"---"}}]},"metadata":{"date":"2026-06-05","name":"rtl-linting","author":"@skillopedia","source":{"stars":1176,"repo_name":"babysitter","origin_url":"https://github.com/a5c-ai/babysitter/blob/HEAD/library/specializations/fpga-programming/skills/rtl-linting/SKILL.md","repo_owner":"a5c-ai","body_sha256":"cb636d9adf41adb4083ea114d44439aede6ac9e0fd8a05c646f7df9938a4fdf3","cluster_key":"d42ef861d89a002f58da8fa63e054bd4a079d8053ad98590c716528a1926c4f8","clean_bundle":{"format":"clean-skill-bundle-v1","source":"a5c-ai/babysitter/library/specializations/fpga-programming/skills/rtl-linting/SKILL.md","attachments":[{"id":"5706da41-3d24-5efe-af45-1a5205b3b0de","key":"uploads/10433ee7-ad12-4ae0-b34e-97553e46c6c8/5706da41-3d24-5efe-af45-1a5205b3b0de/attachment.md","path":"README.md","size":6781,"sha256":"6551e60983db374ebc0b215e71845f340068dc2c01b0463f1fe570e3814d90ed","contentType":"text/markdown; charset=utf-8"}],"bundle_sha256":"c60ffab505d29e34c7ec658486ebbe0515d0c37256ccc5bb2891f833cd6acbf6","attachment_count":1,"text_attachments":1,"attachment_storage":"skillopedia-attachments-v1","binary_attachments":0,"excluded_attachments":[]},"cluster_size":1,"skill_md_path":"library/specializations/fpga-programming/skills/rtl-linting/SKILL.md","import_metadata":{"date":"2026-06-05","author":"@skillopedia","version":"v1","category":"software-engineering","category_label":"Engineering"},"exact_dupes_collapsed_into_this":0},"version":"v1","category":"software-engineering","import_tag":"clean-skills-v1","description":"RTL code quality checking and linting. Runs lint rules, identifies synthesis issues, detects inferred latches, and generates lint reports with waivers.","allowed-tools":"Read, Grep, Write, Edit, Bash, Glob"}},"renderedAt":1782987547536}

Important: agents should read /llm.txt, /llms.txt, or /.well-known/skills.json to discover the public Skillopedia API.