Verilog/SystemVerilog Language Skill Expert skill for Verilog and SystemVerilog development following IEEE 1364 and IEEE 1800 standards. Provides deep expertise in synthesizable RTL code generation, proper construct usage, and modern coding practices. Overview The Verilog/SystemVerilog Language skill enables comprehensive HDL development for FPGA and ASIC designs, supporting: - IEEE 1800-2017 SystemVerilog standard - Verilog-2005 backward compatibility - Proper always ff, always comb, always latch usage - SystemVerilog interfaces and modports - Parameterized modules with localparam - Packed a…